The present invention relates to a drive circuit and, more particularly, to such a circuit fabricated as a semiconductor integrated circuit (IC) for driving an electroluminescent (CL) display panel.
As well known in the art, a few hundred volts are required to drive the EL display panel. For this reason, a drive circuit for the EL display panel was constructed to employ discrete semiconductor elements such as thyristors.
However, high withstand device structure and process has been recently developed and put into practical use. A drive circuit fabricated as an IC has become available.
Referring to FIG. 1, such a drive IC 1 is shown. Input signal IN representative of image data to be displayed is supplied in series to an input pin 3 of the IC 1. Connected to the pin 3 is an input data processing circuit 2 which includes a shift register (not shown) for converting the input signal supplied in series into parallel data signals D1 to Dn. These data signals D1 to Dn are supplied to a plurality of output stages 100-1 to 100-n, respectively, which are provided in one-to-one correspondence with the data signals D. Each of the output stages 100 produces and outputs an output signal OUT to a corresponding one of output pins 400-1 to 400-n which are in turn connected directly to the EL display panel (not shown).
As described above, the input signal IN represents image data to be displayed produced by a data processing unit such as microcomputer. Accordingly, the input signal IN has a logic amplitude changing typically between +5 V and 0 V. On the other hand, each output signal OUT directly drives the EL panel and thus each has another logic amplitude changing between a few hundred volts and 0 V. That is, the drive IC 1 is also required to have a level converting function of converting the small logic amplitude of the input signal IN into a required, large logic amplitude.
For this purpose, three power pins 4, 5 and 6 are provided in the drive IC 1. The first power pin 4 is supplied with a first power voltage V.sub.DD1 of 5 V, and the second power pin 5 is supplied with a second power voltage V.sub.DD2 of 200 V, for example. The third power pin 6 is supplied with a ground voltage GND of 0 V. The input data processing unit 2 is connected to the power pins 4 and 6 to deal with the input signal IN. On the other hand, each of the output stages 100-1 to 100-n is connected to the power pins 4, 5 and 6 to perform the level converting function.
Turning to FIG. 2, there is shown a circuit diagram of the output stage 100-1. It should noted that each of the output stages 100-1 to 100-n has the same circuit construction as the others. The output stage 100-1 has a data terminal 30 supplied with an input data signal D1, a first power terminal 40 connected to the pin 4 to receive V.sub.DD1 power voltage, a second power terminal 50 connected to the pin 5 to receive V.sub.DD2 power voltage, a ground terminal 60 connected to the pin 6 to receive ground voltage, and an output terminal 70 connected the pin 400-1 to supply the output data signal OUT 1. The output stage 100-1 further has an inverter INV, three P-channel MOS transistors P101 to P103 and three N-channel MOS transistors N101 to N103 which are connected as shown. In particular, the transistors P101, P102, N101 and N102 constitute a level-shift circuit 10 to drive the output transistors P101 and N103.
As apparent from the circuit construction shown in FIG. 2, the input data signal D1 having a small logic amplitude between V.sub.DD1 level and the ground level is changed to the output signal OUT 1 having a large logic amplitude between the V.sub.DD2 level and the ground, as shown in FIG. 3. The EL display panel is thus driven directly by the drive IC 1.
Since the drive IC 1 is of a complementary MOS (CMOS) construction, power consumption in a steady state in which the input data signal D is in one of two logic states is substantially zero, as well known in the art. That is, no dc current flows between the power terminals 50 and 60 in the steady state. However, as also known in the art, in a transition state in which the signal changes from one logic level to the other logic level, a dc current flows between the power terminals 50 and 60. Moreover, such a dc current is considerably large, because the transistors P101 to N103 are made with a large size to have a high withstand voltage. As a result, there occurs a relatively large voltage change on a ground line GLN (see FIG. 1) due to the impedance thereof during every transistor period, as shown in FIG. 3. This voltage change provides the input data processing unit 2 with a change of the ground voltage. For this reason, the unit 2 is often subjected to the malfunction.